About

Yuva Prasad Nagari is a Design Verification-Trainee Engineer with a passion for electronics and VLSI circuit design. He has a good knowledge of functional verification and has worked on AMBA AXI4 Protocol, developing AXI Slave VIP with all features including basic read and write, outstanding, out of order, and interleaving. He has also verified AXI Master Design and worked on AMBA APB and Ethernet Protocols. Yuva is proficient in Verilog, SV, and UVM and has hands-on experience with Cadence Tool. He is also skilled in Perl scripting and Linux OS commands. Yuva completed a 1-month academic research internship in VLSI circuit design using Cadence at IIITDM, Kancheepuram. He is interested in working and researching in the core points of electronics and VLSI. Yuva has worked as a Design Verification Trainee Engineer at Moschip Institute of Silicon Systems (M-ISS), where he gained knowledge in Verilog, SV, UVM, and Perl Scripting. He worked on projects in Verilog, including ALU, Direction Based UP-Down Counter, and projects in SV and UVM, including AMBA APB, AXI4, and Ethernet Protocols. He also worked as an Associate Software Engineer at Accenture. Yuva holds a Bachelor of Technology degree in Electrical, Electronics and Communications Engineering from Madhanapalle Institutes of Technology & Science, which he completed in 2021. He also holds an intermediate degree in MPC from Sai Sri Chaitanya Junior College, which he completed in 2017. With 1.52 years of relevant experience, Yuva is a research scientist and software engineer with a strong interest in electronics and VLSI circuit design.